Patent
Quantum bit array
| العنوان: | Quantum bit array |
|---|---|
| Patent Number: | 11723,288 |
| تاريخ النشر: | August 08, 2023 |
| Appl. No: | 17/209107 |
| Application Filed: | March 22, 2021 |
| مستخلص: | A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel. |
| Inventors: | Hsu, Fu-Chang (San Jose, CA, US); Hsu, Kevin (San Jose, CA, US) |
| Claim: | 1. A quantum bit array comprising: a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array; a bit line; a first transistor channel that connects the bit line to the control gate; at least one word line coupled to the first transistor channel, wherein the at least one word line selectively controls charge flow through the first transistor channel; and a capacitor coupled to selectively maintain charge in the first transistor channel when the at least one word line is deselected. |
| Claim: | 2. The array of claim 1 , wherein the first transistor channel forms a vertical transistor channel and the at least one word line forms at least one horizontal word line. |
| Claim: | 3. The array of claim 1 , wherein the capacitor comprises a vertical MOS capacitor. |
| Claim: | 4. The array of claim 1 , wherein the first transistor channel is directly connected to the control gate. |
| Claim: | 5. The array of claim 1 , further comprising a contact that connects the first transistor channel to the control gate. |
| Claim: | 6. The array of claim 1 , wherein the first transistor channel comprises a gate dielectric layer. |
| Claim: | 7. The array of claim 1 , wherein the first transistor channels forms a junction-less transistor. |
| Claim: | 8. The array of claim 1 , wherein the first transistor channel comprises a source junction and a drain junction. |
| Claim: | 9. The array of claim 1 , wherein the first transistor channel comprises an insulating core. |
| Claim: | 10. The array of claim 1 , wherein the at least one word line comprises an X-direction word line and a Y-direction word line. |
| Claim: | 11. The array of claim 1 , wherein the array further comprises: a second transistor channel that connects a second bit line to a first pass gate; and a third transistor channel that connects a third bit line to a second pass gate. |
| Claim: | 12. The array of claim 11 , further comprising: a second capacitor configured to store charge in the second transistor channel; and a third capacitor configured to store charge in the third transistor channel. |
| Claim: | 13. The array of claim 12 , wherein the at least one word line comprises one X-direction word line coupled to the first, second, and third transistor channels and one Y-direction word line coupled to the first, second, and third transistor channels. |
| Claim: | 14. The array of claim 12 , wherein the at least one word line comprises two X-direction word lines coupled to the first, second, and third transistor channels and two Y-direction word lines coupled to the first, second, and third transistor channels. |
| Claim: | 15. The array of claim 12 , wherein the at least one word lines comprise first, second and third X-direction word lines coupled one-to-one to the first, second, and third transistor channels, respectively, and one Y-direction word line coupled to the first, second, and third transistor channels. |
| Claim: | 16. A method for operating a quantum array, the method comprising: applying one or more first voltages to one or more Y-direction word lines that are coupled to at least one vertical transistor, respectively; applying one or more second voltages to one or more X-direction word lines that are coupled to the at least one vertical transistor, respectively; applying a third voltage to a capacitor that is coupled to the at least one vertical transistor to selectively maintain charge in at least one channel when word lines coupled to the at least one vertical transistor are deselected; and applying one or more bit line voltages to the at least one vertical transistor to control operations of a qubit of the quantum array. |
| Claim: | 17. The method of claim 16 , wherein the operation of applying one or more first voltages comprises applying a selected first voltage to one X-direction word line coupled to the at least one vertical transistor, and wherein the operation applying one or more second voltages comprises applying a selected second voltage to one Y-direction word line coupled to the plurality of transistor channels at least one vertical transistor. |
| Claim: | 18. The method of claim 16 , wherein the operation of applying one or more first voltages comprises applying two selected first voltages to two X-direction word lines coupled to the at least one vertical transistor, and wherein the operation applying one or more second voltages comprises applying two selected second voltages to two Y-direction word lines coupled to the plurality of transistor channels. |
| Claim: | 19. The method of claim 16 , wherein the operation of applying one or more first voltages comprises applying at least one selected voltage to at least one X-direction word lines coupled to the at least one vertical transistor, respectively, and wherein the operation applying one or more second voltages comprises applying one selected second voltage to one Y-direction word line coupled to the plurality of transistor channels. |
| Claim: | 20. The method of claim 16 , further comprising: removing the one or more first voltages from the one or more Y-direction word lines; and removing the one or more second voltages from the one or more X-direction word lines, wherein the capacitor is isolated and maintains a charge in at least one channel of the at least one vertical transistor, respectively. |
| Patent References Cited: | 20120280208 November 2012 Jain 20160087212 March 2016 Klein 20160125311 May 2016 Fuechsle 20180226451 August 2018 Dzurak et al. 20180301381 October 2018 Bi et al. WO 2017/150980 September 2017 WO 2019/066843 April 2019 |
| Other References: | International Search Report, dated Jun. 8, 2021, for corresponding International Application No. PCT/US2021/023534, pp. 1-2. cited by applicant Written Opinion of the International Searching Authority, dated Jun. 8, 2021, for corresponding International Application No. PCT/US2021/023534, pp. 1-6. cited by applicant First Examination Report, dated Jan. 24, 2023, for corresponding India Application No. 202227059540 (total 7 pages). cited by applicant |
| Primary Examiner: | Skibinski, Tomi |
| Attorney, Agent or Firm: | Intellectual Property Law Group LLP |
| رقم الانضمام: | edspgr.11723288 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |