Patent
Methods and apparatuses for adaptive dynamic voltage control for optimizing energy per operation per a given target speed
| العنوان: | Methods and apparatuses for adaptive dynamic voltage control for optimizing energy per operation per a given target speed |
|---|---|
| Patent Number: | 9,935,542 |
| تاريخ النشر: | April 03, 2018 |
| Appl. No: | 15/060988 |
| Application Filed: | March 04, 2016 |
| مستخلص: | A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SOFTWARE programmable Adaptive Dynamic Voltage Control (ADVC) algorithm using different sensors inside the chip in order to improve the target speed and reduce the energy per operation of the final product. This method achieves the best power per performance for a given solution operating at a required speed. |
| Inventors: | Zangi, Uzi (Hod-Hasharon, IL); Feldman, Neil (Misgav, IL) |
| Assignees: | PLSense Ltd. (Yokneam Elit, IL) |
| Claim: | 1. A Semiconductor Integrated Circuit device comprising: multiple sensors located on the Semiconductor Integrated Circuit device, said multiple sensors being selected from temperature sensors, process monitor sensors, transistor threshold voltage monitor; a first fail circuit designed to be worst case paths of a logic design of the device; a CPU operating a SOFTWARE algorithm, said CPU controls operating voltage of different blocks inside the device on the fly according to results from the SOFTWARE algorithm, the CPU reads the multiple sensors and operates the first fail circuit to determine the correct operational voltage level of the different blocks inside the device; wherein the first fail circuit is connected to a second power source separate from the power source of the Semiconductor Integrated Circuit device, said second power source is controlled by the CPU without influencing the rest of the logic voltage, the SOFTWARE adjusts the voltage level until the first fail circuit goes from non-functional state to functional state, the CPU utilizes this information to know a lowest optimal voltage needed for the design to operate correctly; wherein the Semiconductor integrated Circuit device is operating in the Near or Sub threshold region; and wherein a design of the Semiconductor Integrated Circuit device includes two programmable operating voltage sources. |
| Claim: | 2. The device of claim 1 wherein the Semiconductor Integrated Circuit device is operating in the Near or Sub threshold region with an operating voltage level based upon determined performance requirements and the input samples from the on device sensors. |
| Claim: | 3. The device of claim 1 wherein the Semiconductor Integrated Circuit device includes one or more logic cells or/and SRAM (memory) cells capable of operating in the Near or Sub threshold voltage levels and wherein one or more logic cells or SRAM cells are characterized to run at the required performance and the operating voltage. |
| Claim: | 4. The device of claim 1 wherein a design of the Semiconductor Integrated Circuit device includes one or more sensors for process monitoring, temperature sensing and other sensors. |
| Claim: | 5. The device of claim 4 wherein the sensors can be read by an integrated or external CPU. |
| Claim: | 6. The device of claim 1 wherein the two programmable operating voltage sources are controlled via a SOFTWARE algorithm running on the CPU. |
| Claim: | 7. The device of claim 1 wherein a design of the Semiconductor Integrated Circuit device includes one or more first fail circuitries with an operating voltage source that is different than the rest of the devices voltage source and can be controlled through the SOFTWARE algorithm running on the CPU. |
| Claim: | 8. The device of claim 7 wherein the design of the one or more first fail circuits is to implement the worst case timing path of the logic design of a specific device. |
| Claim: | 9. The device of claim 8 wherein few different delay lines exist in the first fail circuit to implement the worst case timing path of the logic design, both for timing paths with short wires between circuitries and for timing paths with long wires between circuitries. |
| Claim: | 10. The device of claim 1 wherein the SOFTWARE algorithm combines the inputs from the multiple sensors inside the device and the results from the lowest operating voltage at which the first fail circuitry still operates correctly and uses the inputs to adjust dynamically and adaptively the operating voltage of the device to the lowest possible voltage at which the device still operates correctly. |
| Patent References Cited: | 6522182 February 2003 Tomita 6967522 November 2005 Chandrakasan 7973594 July 2011 Amrutur 8502590 August 2013 Friddell 9244515 January 2016 Kawasaki 2012/0159276 June 2012 Zandian 2013/0222018 August 2013 Park 2014/0070879 March 2014 Kawasaki 2014/0176189 June 2014 Wang 2014/0247088 September 2014 Prager 2014/0250313 September 2014 Marr 2016/0013792 January 2016 Ashouei 2016/0105162 April 2016 Zangi 2016/0283630 September 2016 Zangi |
| Primary Examiner: | Rossoshek, Helen |
| رقم الانضمام: | edspgr.09935542 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |