Patent
Methods and apparatuses for sub-threhold clock tree design for optimal power
| العنوان: | Methods and apparatuses for sub-threhold clock tree design for optimal power |
|---|---|
| Patent Number: | 9,768,775 |
| تاريخ النشر: | September 19, 2017 |
| Appl. No: | 14/923743 |
| Application Filed: | October 27, 2015 |
| مستخلص: | A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage. |
| Inventors: | Zangi, Uzi (Hod-Hasharon, IL); Feldman, Neil (Misgav, IL) |
| Assignees: | PLSense Ltd. (Hod-Hasharon, IL) |
| Claim: | 1. An ASIC, comprising: a plurality of logic cells operating in a near-threshold or sub-threshold voltage domain; a clock tree comprising a plurality of transistors operating at a voltage range having a minimal value of zero and a maximal value at the near-threshold or sub-threshold voltage domain, wherein clock signals propagate in the clock tree and drive the clocks of flip flops located in the plurality of logic cells; wherein a voltage domain in which the clock tree is operating is slightly higher than a voltage domain in which the plurality of logic cells are operating, wherein the clock tree further comprises buffers; a voltage level of the clock tree buffers is defined in accordance with the number of flip flops within the ASIC. |
| Claim: | 2. The ASIC of claim 1 , wherein the plurality of transistors operate in more than one voltage domain residing in a near-threshold or sub-threshold region. |
| Claim: | 3. The ASIC of claim 1 , wherein the slightly higher voltage domain used by the clock tree is utilized to achieve better performance in the ASIC. |
| Claim: | 4. The ASIC of claim 3 , wherein a voltage difference between the voltage domains omits a need to translate logic levels between the clock tree and the other component of the ASIC. |
| Claim: | 5. The ASIC of claim 1 , wherein the clock tree resides in a dedicated Place and Route implementation. |
| Claim: | 6. The ASIC of claim 1 , wherein other transistors outside the clock tree reside in the same dedicated Place and Route implementation. |
| Claim: | 7. The ASIC of claim 1 , wherein the clock tree comprises fan-out outlines. |
| Claim: | 8. The ASIC of claim 7 , wherein the voltage level of the clock tree buffers is determined according to the number of flip flops residing in a fan-out fashion. |
| Claim: | 9. The ASIC of claim 8 , wherein the voltage level of the clock tree buffers is selected based on the number of flip flops in a block and the required fan-out of the clock tree buffers. |
| Claim: | 10. The ASIC of claim 9 , wherein the voltage level of the clock tree buffers is selected in order to optimize the total number of buffers at the clock tree and this also optimize the power consumption. |
| Claim: | 11. The ASIC of claim 7 , further comprises components that use the clock tree to evenly distribute the clock signals between the components inside the ASIC. |
| Claim: | 12. An ASIC, comprising: a plurality of logic cells operating in a near-threshold or sub-threshold voltage domain; a clock tree comprising a plurality of transistors operating at a voltage range having a minimal value of zero and a maximal value at the near-threshold or sub-threshold voltage domain, wherein clock signals propagate in the clock tree and drive the clock of flip flops located in the plurality of logic cells; wherein the voltage domain in which the clock tree is operating is slightly higher than a voltage domain in which the plurality of logic cells are operating; wherein the clock tree comprises fan-out outlines; and buffers, and wherein a voltage level of the clock tree buffers is determined according to the number of flip flops residing in a fan-out fashion. |
| Claim: | 13. The ASIC of claim 12 , wherein the plurality of transistors operate in more than one voltage domain residing in a near-threshold or sub-threshold region. |
| Claim: | 14. The ASIC of claim 12 , wherein the slightly higher voltage domain used by the clock tree is utilized to achieve better performance in the ASIC. |
| Claim: | 15. The ASIC of claim 14 , wherein a voltage difference between the voltage domains omits a need to translate logic levels between the clock tree and the other component of the ASIC. |
| Claim: | 16. The ASIC of claim 12 , wherein the clock tree resides in a dedicated Place and Route implementation. |
| Claim: | 17. The ASIC of claim 12 , wherein other transistors outside the clock tree reside in the same dedicated Place and Route implementation. |
| Claim: | 18. The ASIC of claim 12 , wherein the voltage level of the clock tree buffers is selected based on the number of flip flops in a block and the required fan-out of the clock tree buffers. |
| Claim: | 19. The ASIC of claim 18 , wherein the voltage level of the clock tree buffers is selected in order to optimize the total number of buffers at the clock tree and this also optimize a power consumption. |
| Claim: | 20. The ASIC of claim 12 , further comprises components that use the clock tree to evenly distribute the clock signals between the components inside the ASIC. |
| Patent References Cited: | 7477073 January 2009 Tuan 2008/0129362 June 2008 Kawai 2013/0154686 June 2013 Chan 2013/0159757 June 2013 Park 2013/0214816 August 2013 Thornton 2014/0266369 September 2014 Brunolli 2015/0188519 July 2015 Singhal |
| Assistant Examiner: | Cho, James H |
| Primary Examiner: | Owens, Douglas W |
| رقم الانضمام: | edspgr.09768775 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |