التفاصيل البيبلوغرافية
| العنوان: |
Pipelined digital filters and their applications:fdatool design and verilog HDL verification |
| المؤلفون: |
Lai, P. H. (Phuong H.), Nguyen, T. V. (Tung V.), Ta, K. D. (Khoa D.), Truong, T. V. (Thien V.), Nguyen, D. B. (Duong B.), Nguyen, P. H. (Phong H.) |
| بيانات النشر: |
World Academy of Research in Science and Engineering |
| سنة النشر: |
2020 |
| المجموعة: |
Jultika - University of Oulu repository / Oulun yliopiston julkaisuarkisto |
| مصطلحات موضوعية: |
Application specific integrated design (ASIC), FIR, IIR, MATLAB fdatool, Model Simulation, VerilogHDL, digital filters, digital system design |
| الوصف: |
This research will provide system on chip design for pipelined digital filters module. Two basic but important FIR and IIR filters are going to be discussed. At first, the position of digital filters in digital system is explained. Then, MATLAB fdatool and scripts are used for filter design. Finally, the implementation and verification of proposed filter processor are performed VERILOG hardware description language (HDL).All scripts, algorithm is clearly given. We hope that the research will be a great reference and an intellectual property core for engineers and researcher students. |
| نوع الوثيقة: |
article in journal/newspaper |
| وصف الملف: |
application/pdf |
| اللغة: |
English |
| الإتاحة: |
http://urn.fi/urn:nbn:fi-fe202101283009Test |
| حقوق: |
info:eu-repo/semantics/openAccess ; © The Authors 2020. |
| رقم الانضمام: |
edsbas.A7DF43A5 |
| قاعدة البيانات: |
BASE |
