التفاصيل البيبلوغرافية
| العنوان: |
Analysis and implementation of sdf radix-2 fft processor using verilog hardware description language |
| المؤلفون: |
Lai, P. H. (Phuong H.), Hoang, M. (Manh), Tran, V. Q. (Viet Q.), Nguyen, T. V. (Tung V.), Truong, T. V. (Thien V.), Nguyen, P. H. (Phong H.) |
| بيانات النشر: |
The World Academy of Research in Science and Engineering |
| سنة النشر: |
2020 |
| المجموعة: |
Jultika - University of Oulu repository / Oulun yliopiston julkaisuarkisto |
| مصطلحات موضوعية: |
FPGA, Fourier transform, Pipeline processor, System on Chip design, VERILOG HDL |
| الوصف: |
This paper will study a novel system on chip (SoC) design for fast Fourier transform (FFT) module. We first explain the role and position of FFT module in a digital intelligent system. Then, the discrete Fourier transform (DFT) and decimation in frequency (DIF) Radix-2 butterfly FFT algorithm is explained in detail, mathematically. In addition, the analysis of a simple pipeline FFT processor and a single-path delay feedback pipeline FFT processor based on SDF Radix-2 algorithm are discussed. Finally, the implementation and verification of proposed FFT processor are performed VERILOG hardware description language (HDL). |
| نوع الوثيقة: |
article in journal/newspaper |
| وصف الملف: |
application/pdf |
| اللغة: |
English |
| الإتاحة: |
http://urn.fi/urn:nbn:fi-fe2020112092225Test |
| حقوق: |
info:eu-repo/semantics/openAccess ; © The Authors 2020. |
| رقم الانضمام: |
edsbas.36898315 |
| قاعدة البيانات: |
BASE |
