دورية أكاديمية
Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface
| العنوان: | Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface |
|---|---|
| المؤلفون: | Baungarten Leon, Emilio, Martin del Campo Becerra, Gustavo Daniel, Ortega Cisneros, Susana, Schlemon, Maron, Rivera, Jorge, Reigber, Andreas |
| بيانات النشر: | Multidisciplinary Digital Publishing Institute (MDPI) |
| سنة النشر: | 2023 |
| المجموعة: | German Aerospace Center: elib - DLR electronic library |
| مصطلحات موضوعية: | SAR-Technologie |
| الوصف: | This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access. |
| نوع الوثيقة: | article in journal/newspaper |
| وصف الملف: | application/pdf |
| اللغة: | English |
| العلاقة: | https://elib.dlr.de/193020/1/electronics-12-02558.pdfTest; Baungarten Leon, Emilio und Martin del Campo Becerra, Gustavo Daniel und Ortega Cisneros, Susana und Schlemon, Maron und Rivera, Jorge und Reigber, Andreas (2023) Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface. Electronics, 12 (12). Multidisciplinary Digital Publishing Institute (MDPI). doi:10.3390/electronics12122558 . ISSN 2079-9292. |
| الإتاحة: | https://doi.org/10.3390/electronics12122558Test https://elib.dlr.de/193020Test/ https://elib.dlr.de/193020/1/electronics-12-02558.pdfTest https://www.mdpi.com/journal/electronicsTest |
| حقوق: | cc_by |
| رقم الانضمام: | edsbas.2DC99046 |
| قاعدة البيانات: | BASE |
| الوصف غير متاح. |