Jaguar: A next-generation low-power x86-64 core

التفاصيل البيبلوغرافية
العنوان: Jaguar: A next-generation low-power x86-64 core
المؤلفون: Teja Singh, Shane Southard, Joshua A. Bell
المصدر: ISSCC
بيانات النشر: IEEE, 2013.
سنة النشر: 2013
مصطلحات موضوعية: Engineering, Power gating, CPU cache, business.industry, Parallel computing, Modular design, computer.software_genre, Power optimization, Power (physics), Low-power electronics, Operating system, x86, System on a chip, business, computer
الوصف: “Jaguar” (JG) is the codename for AMD's follow-on project to the low-power x86-64 core, codenamed “Bobcat” (BT). AMD's first 28nm × 86 processor, the 3.08mm2 JG core is designed to support a wide range of applications from low-power tablets requiring sub-5W SoCs to client products up to 25W. Similar to BT, the JG core uses integrated power gating to provide a low-power state for SOC power optimization. A JG compute unit (CU) is constructed using 4 JG cores, four 0.5MB L2 cache modules and an L2 interface (Fig. 3.4.1). An initial SOC has one 26.2mm2 CU, but AMD's modular design approach allows for different SOC configurations.
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_________::b570c3c038fbc801d15ba6e3ef6655f7Test
https://doi.org/10.1109/isscc.2013.6487633Test
رقم الانضمام: edsair.doi...........b570c3c038fbc801d15ba6e3ef6655f7
قاعدة البيانات: OpenAIRE