An alternative technique to improve the electric performance of shrunk MOSFET devices is strained engineering. Considering SiGe channel layer as a global strain capping a Si layer to prevent Ge diffusion from the SiGe channel layer and soften the stress between SiON gate dielectric and SiGe channel is a possible way. To favor NMOSFET, depositing silicon nitride on gate as contact etching stop layer (CESL) process providing the tensile effect is more appreciated. In this study, besides the electrical characteristics with different strain processes, the conduction path and channel location of electron carrier through body bias adjustment is an attractive exploration. Because the charge profile in channel shown as a quantum mechanical effect is not a uniform distribution, the chief inversion layer thickness of electron carrier will be shifted when the substrate bias is applied. This evidence will be exhibited in gamma factor. Observing the gamma shift, the main conductive path of electron carrier can be diagnosed and analyzed about the quality of SiGe layer in growth.
