A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process
العنوان: | A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process |
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المؤلفون: | S. Yamakawa, Y. Yoneda, Takaaki Murakami, Hiroomi Ueda, Tatsuo Oomori, Eiji Taniguchi, Kazuyuki Sugahara, Takahiro Ohnakado, Yasushi Hashizume, M. Ono, Akihiko Furukawa, Jun Tomisawa, Noriharu Suematsu, K. Nishikawa |
المصدر: | IEEE Electron Device Letters. 24:192-194 |
بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2003. |
سنة النشر: | 2003 |
مصطلحات موضوعية: | Materials science, business.industry, Transistor, Electrical engineering, Biasing, Integrated circuit layout, Capacitance, Diffusion capacitance, Electronic, Optical and Magnetic Materials, law.invention, CMOS, law, MOSFET, Insertion loss, Electrical and Electronic Engineering, business |
الوصف: | An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET. |
تدمد: | 1558-0563 0741-3106 |
الوصول الحر: | https://explore.openaire.eu/search/publication?articleId=doi_________::418fe01cc9c464c5c63dad87b52c2518Test https://doi.org/10.1109/led.2003.811404Test |
حقوق: | CLOSED |
رقم الانضمام: | edsair.doi...........418fe01cc9c464c5c63dad87b52c2518 |
قاعدة البيانات: | OpenAIRE |
تدمد: | 15580563 07413106 |
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