يعرض 1 - 10 نتائج من 15 نتيجة بحث عن '"Ramírez Silva, Ana Beatriz"', وقت الاستعلام: 0.93s تنقيح النتائج
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    المساهمون: Ecopetrol, Universidad Industrial de Santander, Purdue University

    المصدر: Ingeniería y Ciencia - ing.cienc.; Vol. 11, Núm. 21 (2015): 10 años; 221-238 ; instname:Universidad EAFIT ; reponame:Repositorio Institucional Universidad EAFIT

    وصف الملف: application/pdf; text/html

    العلاقة: Ingeniería y Ciencia - ing.cienc.; Vol. 11, Núm. 21 (2015): 10 años; 221-238; http://publicaciones.eafit.edu.co/index.php/ingciencia/article/view/2561Test; 1794–9165; http://hdl.handle.net/10784/5299Test

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    المصدر: Ingeniería e Investigación; Vol. 30 No. 1 (2010); 64-70 ; Ingeniería e Investigación; Vol. 30 Núm. 1 (2010); 64-70 ; 2248-8723 ; 0120-5609

    وصف الملف: application/pdf; text/html

    العلاقة: https://revistas.unal.edu.co/index.php/ingeinv/article/view/15209/16003Test; https://revistas.unal.edu.co/index.php/ingeinv/article/view/15209/34103Test; Ach., Achronix Semiconductor Corporation, 2009. Disponible en: http://www.achronix.comTest/. Consultado Marzo de 2009.; Act., Actel Power Matters., 2009. Disponible en: http://www.actel.comTest/. Consultado Marzo de 2009.; Alt., Altera Corporation., 2009. Disponible en: http://www.altera.comTest/. Consultado Marzo de 2009.; Altera Corporation., Stratix IV Device Family Overview., 2008. Disponible en: http://www.altera.com/literature/hb/stratix-iv/stx4siv51001.pdfTest; Altera Corporation., Stratix III Device Family Overview., 2009. Disponible en: http://www.altera.com/literature/hb/stx3/stx3siii51001.pdfTest; Anghelescu, P., Ionita, S., Sofron, E., FPGA implementation of hybrid additive programmable cellular automata encryption algorithm, in HIS 08: Proceedings of the 2008 8th International Conference on Hybrid Intelligent, Systems, IEEE Computer Society, Washington, D.C., USA, 2008, pp. 96-101.; Anghelescu, P., Sofron, E., Rincu, C.-I., Lana, V.-G., Programmable cellular automata based encryption algorithm, Semiconductor Conference, CAS 2008, International 2, 2008, pp. 351-354.; Atm., Atmel Corporation., 2009. Disponible en: http://www.atmel.comTest/. Consultado Marzo de 2009.; Baker, Z. K., Prasanna, V. K., Time and area efficient pattern matching on fpgas, in FPGA 04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, ACM, New York, N.Y., USA, 2004, pp. 223-232.; Beauchamp, M. J., Hauck, S., Underwood, K. D., Hemmert, K. S., Embedded floating-point units in FPGAs, in FPGA 06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, ACM, New York, N.Y., USA, 2006, pp. 12-20.; Bogdán, I. A., Rivers, J., Beynon, R. J., Coca, D., High performance hardware implementation of a parallel database search engine for real-time peptide mass fingerprinting., Bioinformatics, 24(13), 2008, pp. 1498-1502.; Cho, Y. H., Mangione-Smith, W. H., Deep network packet filter design for reconfigurable devices., Trans. On Embedded Computing Sys., 7(2), 2008, pp. 1-26.; Cho, Y., Mangione-Smith, W., Fast reconfiguring deep packet filter for 1+ gigabit network., Field-Programmable Custom Computing Machines, FCCM 2005, 13th Annual IEEE Symposium, 2005, pp. 215-224.; Claerbout, J. F., Green, I., Basic Earth Imaging., Stanford University, 2008a, pp. 60-61.; Claerbout, J. F., Green, I., Basic Earth Imaging., Stanford University., 2008b., pp. 125-128.; Craven, S., Athanas, P., Examining the viability of FPGA supercomputing, EURASIP J. Embedded Syst., No. 1, 2007, pp. 13-13.; CWP., Center for wave phenomena colorado school of Mines., 2009. Disponible en: http://www.cwp.mines.edu/cwpcodesTest/. Consultado en marzo de 2009.; Dido, J., Geraudie, N., Loiseau, L., Payeur, O., Savaria, Y., Poirier, D., A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPS, in FPGA 02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, ACM, New York, N.Y., USA, 2002, pp. 50-55.; GEO., Geocluster Seismic Processing System., 2009. Disponible en: http://www.cggveritas.com/default.aspx?cid=13Test. Consultado Marzo de 2009.; He, C., Lu, M., Sun, C., Accelerating seismic migration using FPGA-based coprocessor platform, in FCCM 04: Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, Washington, D.C., USA, 2004, pp. 207-216.; He, C., Sun, C., Lu, M., Zhao, W., Prestack Kirchhoff time migration on high performance reconfigurable computing platform, SEG Technical Program Expanded Abstracts, Vol. 24, No. 1, 2005, pp. 1902-1905. Disponible en: http://link.aip.org/link/?SGA/24/1902/1Test; Hoang, D. T., Lopresti, D. P., FPGA implementation of systolic sequence alignment., in International Workshop on Field Programmable Logic and Applications, 1993.; Jean, J., Liang, X., Drozd, B., Tomko, K., Accelerating an ir automatic target recognition application with FPGAs., in FCCM 99: Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, Washington, D.C., USA, 1990, pp. 290.; Lat., Lattice Semiconductor Corporation., 2009. Disponible en: http//:www.latticesemi.com/. Consultado Marzo de 2009.; OME., Omega Seismic Processing System., 2009. Disponible en: http://www.westerngeco.com/content/services/dp/omega/index.aspxTest Consultado Marzo de 2009.; Panetta, J., de Souza Filho, P. R. P., da Cunha Filho, C. A., da Motta, F. M. R., Pinheiro, S. S., Junior, I. P., Rosa, A. L. R., Monnerat, L. R., Carneiro, L. T., de Albrecht, C. H. B., Computational characteristics of production seismic migration and its performance on novel processor architectures., in in Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing, IEEE Computer Society, 2007.; Patterson, C., High performance des encryption in virtex(tm) FPGAs using jbits(tm), in FCCM 00: Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, Washington, D.C., USA, 2000, pp. 113.; PRO., ProMAX Seismic Processing Family, 2009. Disponible en: http://www.halliburton.com/ps/default.aspx?pageid=.862n&navid=221n&prodid=MSE::1055450737429153Test. Consultado Marzo de 2009.; Puttegowda, K., Worek, W., Pappas, P., Dandapani, A., Athanas, P., Dickerman, A., A run-time reconfigurable system for gene-sequence searching, in Proceedings of the 16th International Conference on VLSI Design, IEEE Computer Society, 2003, pp. 561-566.; Qui., Quicklogic., 2009. Disponible en: http://www.quicklogic.comTest/. Consultado Marzo de 2009. SEI., Seisup Seismic Processing System., 2009. Disponible en: http://www.geocenter.com/seisup/seisup.htmlTest. Consultado Marzo de 2009.; Sinnappan, R., Hazelhurst, S., A reconfigurable approach to packet filtering, in FPL 01: Proceedings of the 11th International Conference on Field-Programmable Logic and Applications., Springer-Verlag, London, UK, 2001, pp. 638-642.; Sloan, J., High Performance Linux Clusters with OSCAR, Rocks, OpenMosix, and MPI (Nutshell Handbooks), OReilly Media, Inc., 2004. Disponible en: http://www.amazon.ca/exec/obidos/redirect?tag=citeulike09-20&path=ASIN/0596005709Test.; Tessier, R., Burleson, W., Reconfigurable computing for digital signal processing: A survey., Journal of VLSI Signal Processing, 28, 2001, pp. 7-27.; TSU., Tsunami development., 2009. Disponible en: http://www.tsunamidevelopment.com/prestacktimemig.phpTest. Consultado Marzo de 2009.; Underwood, K., FPGAs vs. cpus: trends in peak floating-point performance., in FPGA 04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, ACM, New York, N.Y., USA, 2004, pp. 171-180.; Underwood, K., Hemmert, K., Closing the gap: Cpu and fpga trends in sustainable floating-point blas performance., Field Programmable Custom Computing Machines, FCCM 2004. 12th Annual IEEE Symposium, 2004, pp. 219-228.; USP., Us patent 6,996,470, 2009. Disponible en: http://www.patentstorm.us/patents/6996470.htmlTest. Consultado Marzo de 2009.; Villasenor, J., Schoner, B., Chia, K.-N., Zapata, C., Kim, H. J., Jones, C., Lansing, S., Mangione-Smith, B., Configurable computing solutions for automatic target recognition., FPGAs for Custom Computing Machines, Proceedings IEEE Symposium, 2006, pp. 70-79.; Wang, Y., Shen, Y., Optimized fpga realization of digital matched filter in spread spectrum communication systems., in CITWORKSHOPS 08: Proceedings of the 2008 IEEE 8th International Conference on Computer and Information Technology Workshops, IEEE Computer Society, Washington, D.C., USA, 2008, pp. 173-176.; Xil., Xilinx website., 2009. Disponible en: http://www.xilinx.comTest/. Consultado Marzo de 2009.; Xilinx Inc., AccelDSP Synthesis Tool, User Guide., 2008a. Disponible en: http://www.xilinx.com/support/documentation/swTest manuals/acceldsp user.pdf; Xilinx Inc., ChipScope Pro 10.1 Software and Cores, User Guide., v10.1 edn., 2008 b. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/chipscopeproswcores101ug029.pdfTest; Xilinx Inc., EDK Concepts, tools, and Techniques., 2008c. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/edkctt.pdfTest; Xilinx Inc., PlanAhead Tutorial Release 10.1., 2008d. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/PlanAhead10-1Tutorial.pdfTest; Xilinx Inc., Xilinx ISE 10.1 Design Suite Software Manuals and Help - PDF Collection., 2008e. Disponible en: http://www.xilinx.com/itp/xilinx10/books/manuals.pdfTest; Xilinx Inc., Average ModelSim XE-III Simulation Performance Compared to ModelSim Altera Edition., 2009a. Disponible en: http://www.xilinx.com/ise/verification/mxedetails.html#compareTest; Xilinx Inc., System Generator for DSP Getting Started Guide, User Guide and Reference Guide., 2009b. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/sysgenbklist.pdfTest; Xilinx Inc., Virtex-5 Family Overview., 2009c., Disponible en: http://www.xilinx.com/support/documentation/datasheets/ds100.pdfTest; Xilinx Inc., Virtex-6 Family Overview., 2009d. Disponible en: http://www.xilinx.com/publications/prodmktg/Virtex6Overview.pdfTest; Yamada, M., Nishihara, A., A high-speed fir digital filter with csd coefficients implemented on FPGA., in ASPDAC 01: Proceedings of the 2001 conference on Asia South Pacific design automation, ACM, New York, N.Y., USA, 2001, pp. 7-8.; https://revistas.unal.edu.co/index.php/ingeinv/article/view/15209Test

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    وصف الملف: application/pdf

    العلاقة: http://revistas.unal.edu.co/index.php/ingeinv/article/view/15209Test; Universidad Nacional de Colombia Revistas electrónicas UN Ingeniería e Investigación; Ingeniería e Investigación; Ingeniería e Investigación; Vol. 30, núm. 1 (2010); 64-70 Ingeniería e Investigación; Vol. 30, núm. 1 (2010); 64-70 2248-8723 0120-5609; Abreo Carrillo, Sergio Alberto and Ramírez Silva, Ana Beatriz (2010) Viabilidad de acelerar la migración sísmica 2d usando un procesador específico implementado sobre un fpga. Ingeniería e Investigación; Vol. 30, núm. 1 (2010); 64-70 Ingeniería e Investigación; Vol. 30, núm. 1 (2010); 64-70 2248-8723 0120-5609 .; https://repositorio.unal.edu.co/handle/unal/29207Test; http://bdigital.unal.edu.co/19255Test/; http://bdigital.unal.edu.co/19255/2Test/

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    المصدر: CT&F - Ciencia, tecnología y futuro, ISSN 0122-5383, Vol. 8, Nº. 2, 2018, pags. 99-111

    مصطلحات موضوعية: Inverse theory, Waveform inversion, Numerical modelling

    وصف الملف: application/pdf

    العلاقة: https://dialnet.unirioja.es/servlet/oaiart?codigo=8910617Test; (Revista) ISSN 0122-5383

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