المؤلفون: Sousa, Fernando, Nunes, Fernando

المساهمون: RCIPL

مصطلحات موضوعية: Kalman Filters, Delay Lock Loops, Discriminators, Frequency Locked Loops, Ionospheric Electromagnetic Wave Propagation, Nonlinear Filters, Radio Receivers, Radiowave Propagation, Satellite Navigation

وصف الملف: application/pdf

العلاقة: 978-147993320-4

الإتاحة: http://hdl.handle.net/10400.21/4825Test

المؤلفون: Sousa, Fernando, Nunes, Fernando

المساهمون: RCIPL

مصطلحات موضوعية: Kalman Filters, Delay Lock Loops, Ionospheric Electromagnetic Wave Propagation, Radio Receivers, Radiowave Propagation, Satellite Navigation

وصف الملف: application/pdf

العلاقة: SOUSA, Fernando Manuel Gomes de; NUNES, Fernando D. – Performance analysis of a VDFLL GNSS receiver architecture under ionospheric scintillation and multipath conditions. In IEEE PLANS, Position Location and Navigation Symposium. New York : IEEE - Institute of Electrical and Electronics Engineers Inc., 2014. ISBN: 978-147993320-4. Art. nr. 6851421, p. 602-611.

الإتاحة: http://hdl.handle.net/10400.21/4826Test

المؤلفون: Barajas Ojeda, Enrique, Mateo Peña, Diego, González Jiménez, José Luis

المساهمون: Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

مصطلحات موضوعية: Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal, Delay lock loops, Logic design, Jitter, DLL

وصف الملف: 6 p.; application/pdf

العلاقة: Barajas, E.; Mateo, D.; González, J. DLL's behavioral modeling for power consumption and jitter fast optimization. A: Conference on Design of Circuits and Integrated Systems. "XXV Conference on Design of Circuits and Integrated Systems". Lanzarote (Canaries): 2010, p. 408-413.; http://hdl.handle.net/2117/10525Test

الإتاحة: http://hdl.handle.net/2117/10525Test

المؤلفون: Barajas Ojeda, Enrique, Mateo Peña, Diego, González Jiménez, José Luis

المساهمون: Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

مصطلحات موضوعية: Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal, Logic design, Delay lock loops, DLL behavioural modelling, Jitter optimisation, Processament del senyal

وصف الملف: 7 p.; application/pdf

العلاقة: Barajas, E.; Mateo, D.; González, J. Behavioural modelling of DLLs for fast simulation and optimisation of jitter and power consumption. A: Euromicro Symposium on Digital Systems Design. "13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools". Llille: IEEE Computer Society Publications, 2010, p. 541-547.; http://hdl.handle.net/2117/10678Test

الإتاحة: https://doi.org/10.1109/DSD.2010.86Test
http://hdl.handle.net/2117/10678Test

المؤلفون: Correa, Diego Paolo Ferruzzo, Bueno, Átila Madureira, Piqueira, José Roberto Castilho

المساهمون: Universidade Estadual Paulista (UNESP)

مصطلحات موضوعية: Adaptive gain, Digital PLL, Early Error Sensing time Delay Tan-lock Loop, Fixed-point theorem, Gaussian filter, Synchronism, Fixed point theorems, Gaussian filters, Delay lock loops, Estimation, Frequency estimation, Hardware, Mathematical models, Synchronization, Time delay, Aluminum

وصف الملف: 390-397

العلاقة: Controle y Automacao; http://dx.doi.org/10.1590/S0103-17592011000400006Test; Controle y Automacao, v. 22, n. 4, p. 390-397, 2011.; http://hdl.handle.net/11449/72518Test; S0103-17592011000400006; 2-s2.0-80053923399; 2-s2.0-80053923399.pdf

الإتاحة: https://doi.org/10.1590/S0103-17592011000400006Test
http://hdl.handle.net/11449/72518Test

المؤلفون: Rasheduzzaman, Md., Kimball, Jonathan W.

المصدر: Electrical and Computer Engineering Faculty Research & Creative Works

مصطلحات موضوعية: Delay lock loops, Errors, Harmonic analysis, Locks (fasteners), Mathematical models, Notch filters, Oscillators (electronic), Delays, Frequency measurements, Micro grid, Signal cancellation, Synchronous reference frame, Phase locked loops, Delayed-signal-cancellation, Phase-locked loop, Synchronous reference frame PLL, Electrical and Computer Engineering

العلاقة: https://scholarsmine.mst.edu/ele_comeng_facwork/3928Test; https://doi.org/10.1109/TEC.2018.2880610Test

الإتاحة: https://doi.org/10.1109/TEC.2018.2880610Test
https://scholarsmine.mst.edu/ele_comeng_facwork/3928Test

المؤلفون: Pau Closas, Monica Navarro, Jordi Vila-Valls, Massimo Bertinelli

المساهمون: Centre Tecnològic de Telecomunicacions de Catalunya = Telecommunications Technological Centre of Catalonia (CTTC), Northeastern University [Boston], ESA (Eurpean Space Agency) -Noordwijk (ESA), European Space Agency (ESA), Centre Tecnològic de Telecomunicacions de Catalunya - CTTC (SPAIN), European Space Agency - ESA (THE NETHERLANDS), Northeastern University (USA)

المصدر: IEEE Aerospace and Electronic Systems Magazine
IEEE Aerospace and Electronic Systems Magazine, Institute of Electrical and Electronics Engineers, 2019, 34 (1), pp.16-27. ⟨10.1109/MAES.2019.170208⟩
IEEE AEROSPACE AND ELECTRONIC SYSTEMS MAGAZINE
r-CTTC: Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
r-CTTC. Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
instname

مصطلحات موضوعية: Consultative committee for space data systems, Software radio, Computer science, Signal receivers, Deep space communications, Performance and reliabilities, Deep-space communications, Aerospace Engineering, Phase locked loops, Interplanetary flight, 02 engineering and technology, NASA Deep Space Network, Synchronization, Software reliability, 0203 mechanical engineering, Robustness (computer science), Locks (fasteners), State-of-the-art system, Turbo code, Traitement du signal et de l'image, Wireless communications system, elecommand transponders, Electrical and Electronic Engineering, Low-density parity-check code, 020301 aerospace & aeronautics, Delay lock loops, Signal to noise ratio, Radio receivers, acquisition, Codes (symbols), Transponders, Communication technologies, Phase Locked Loop (PLL), Software-defined radio, Low-density parity-check (LDPC) codes, carrier/symbol tracking, Coding gain, Phase-locked loop, Computer engineering, Bit error rate, Space and Planetary Science, Forward error correction, Systems design, Kalman filter, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, synchronization

وصف الملف: application/pdf

الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::02a540d8894b16418cba789acabb6c86Test
https://zenodo.org/record/3471450Test

المؤلفون: K. Giger and C. Günther

المساهمون: Lehrstuhl für Kommunikation und Navigation

مصطلحات موضوعية: info:eu-repo/classification/ddc, Kalman filters, delay lock loops, phase coding, receivers, satellite navigation

وصف الملف: Text

العلاقة: https://mediatum.ub.tum.de/1078621Test; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5707997Test

الإتاحة: https://mediatum.ub.tum.de/1078621Test
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5707997Test;

المؤلفون: CHEN, XIN, DOVIS, Fabio, PINI, MARCO

المساهمون: Chen, Xin, Dovis, Fabio, Pini, Marco

مصطلحات موضوعية: GNSS multipath, delay lock loops

وصف الملف: ELETTRONICO

العلاقة: info:eu-repo/semantics/altIdentifier/isbn/9781424450367; info:eu-repo/semantics/altIdentifier/isbn/9781424450374; info:eu-repo/semantics/altIdentifier/wos/WOS:000287515800068; ispartofbook:Proceedings of IEEE/ION Position Location and Navigation Symposium (PLANS), 2010; IEEE/ION Position Location and Navigation Symposium (PLANS), 2010; firstpage:1118; lastpage:1126; numberofpages:9; http://hdl.handle.net/11583/2422728Test; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-77955026285; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5507230Test

الإتاحة: https://doi.org/10.1109/PLANS.2010.5507230Test
http://hdl.handle.net/11583/2422728Test
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5507230Test

المؤلفون: Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang

المساهمون: 黃柏鈞

مصطلحات موضوعية: CMOS integrated circuits, circuit stability, delay lock loops, demodulators, frequency shift keying

الوقت: 45

العلاقة: Custom Integrated Circuits Conference, 2007. CICC '07. IEEE, 16-19 Sept. 2007, Pages 217 - 220; http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69643Test

الإتاحة: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69643Test