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81مؤتمر
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Multimedia systems, Parallel processing (Electronic computers), Pipeline processing, Instruction sets, Sistemes multimèdia, Processament en paral·lel (Ordinadors)
وصف الملف: 12 p.
العلاقة: http://ieeexplore.ieee.org/document/953290Test/; Corbal, J., Espasa, R., Valero, M. On the efficiency of reductions in µ-SIMD media extensions. A: International Conference on Parallel Architectures and Compilation Techniques. "2001 International Conference on Parallel Architectures and Compilation Techniques: 8-12 September 2001 Barcelona, Catalunya, Spain: proceedings". Barcelona: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 83-94.; 0-7695-1363-8; http://hdl.handle.net/2117/104030Test
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82مؤتمر
المؤلفون: Aragón, Juan Luis, González, José, García Carrasco, José M., González Colás, Antonio María
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Parallel processing (Electronic computers), Performance evaluation, Parallel architectures, Pipeline processing, Processament en paral·lel (Ordinadors)
وصف الملف: 6 p.; application/pdf
العلاقة: http://ieeexplore.ieee.org/document/955033Test/; Aragón, J., González, J., García, J., González, A. Selective branch prediction reversal by correlating with data values and control flow. A: IEEE International Conference on Computer Design. "2001 International Conference on Computer Design, ICCD 2001: 23-26 September 2001 Austin, Texas, USA: proceedings". Austin, TX: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 228-233.; 0-7695-1200-3; http://hdl.handle.net/2117/102017Test
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83
المؤلفون: MengChao Wu, HuiXing Li, Yizhuang Xie, Hu Shanqing, YangKai Feng, Bingyi Li
المصدر: The Journal of Engineering (2019)
مصطلحات موضوعية: Synthetic aperture radar, Floating point, Computer science, Iterative method, microprocessor chips, azimuthal nonuniform sampling results, Energy Engineering and Power Technology, Inverse, resource allocation, computing unit, resource balancing, single-precision floating-point data type, matrix inversion, law.invention, Computational science, reconfigurable architectures, fpga-based reconfigurable matrix inversion implementation, law, Radar imaging, lu decomposition algorithm, hierarchical iterative processing strategy, multichannel synthetic aperture radar, virtual points, Field-programmable gate array, reusable structure, reconfigurable storage, field programmable gate arrays, multichannel sar imaging, data scheduling, pipeline processing, processor scheduling, pipeline technology, General Engineering, Inversion (meteorology), multichannel preprocessing, matrix inversion method, LU decomposition, floating-point ip cores, floating point arithmetic, radar imaging, inverse filter algorithm, lcsh:TA1-2040, modelsim platform, filtering theory, iterative methods, image sampling, lcsh:Engineering (General). Civil engineering (General), Software, synthetic aperture radar
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::34d85c6374e115b02d0fb023de5c54b6Test
https://digital-library.theiet.org/content/journals/10.1049/joe.2019.0748Test -
84
المصدر: IEEE Access, Vol 6, Pp 72327-72344 (2018)
مصطلحات موضوعية: Multi-core processor, pipeline processing, Speedup, Optimization problem, parallel programming, particle swarm optimization, General Computer Science, Dataflow, Computer science, General Engineering, Field programmable gate arrays, Particle swarm optimization, 020206 networking & telecommunications, 02 engineering and technology, multicore processing, Swarm intelligence, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, General Materials Science, lcsh:Electrical engineering. Electronics. Nuclear engineering, Field-programmable gate array, lcsh:TK1-9971, Algorithm, Throughput (business)
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::968d1b54856720ab0cdaa604a10c459aTest
https://doi.org/10.1109/access.2018.2882455Test -
85
المؤلفون: Mohd Zulkifly Abdullah, Abdul-Malik H. Y. Saad
المصدر: IEEE Access, Vol 6, Pp 71389-71403 (2018)
مصطلحات موضوعية: pipeline processing, General Computer Science, Pixel, Computer science, General Engineering, Digital circuits, parallel architectures, 020207 software engineering, 02 engineering and technology, Reduction (complexity), fractal image compression, Fractal, Fractal compression, Gate array, Stratix, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, General Materials Science, lcsh:Electrical engineering. Electronics. Nuclear engineering, lcsh:TK1-9971, Algorithm, field programmable gate arrays, Block (data storage)
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f55e2791ea02b89dd9b4db6e050e1e63Test
https://doi.org/10.1109/access.2018.2880480Test -
86مؤتمر
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Parallel processing (Electronic computers), VLIW, Registers, Processor scheduling, Delay effects, Communication channels, Proposals, Pipeline processing, Electronic mail, Continuous improvement, Processament en paral·lel (Ordinadors)
وصف الملف: 8 p.
العلاقة: http://ieeexplore.ieee.org/document/876173Test/; Sánchez, F., González, A. The effectiveness of loop unrolling for modulo scheduling in clustered VLIW architectures. A: International Conference on Parallel Processing. "2000 International Conference on Parallel Processing: 21-24 August 2000, Toronto, Canada: proceedings". Toronto: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 555-562.; 0-7695-0768-9; http://hdl.handle.net/2117/105275Test
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87مؤتمر
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Parallel processing (Electronic computers), Pipeline processing, Scheduling, Instruction sets, Performance evaluation, Program control structures, Processament en paral·lel (Ordinadors)
وصف الملف: 6 p.
العلاقة: http://ieeexplore.ieee.org/document/874027Test/; Sánchez, F., González, A. Instruction scheduling for clustered VLIW architectures. A: International Symposium on System Synthesis. "Proceedings: The 13th International Symposium on System Synthesis". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 41-46.; 0-7695-0765-4; http://hdl.handle.net/2117/100204Test
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88مؤتمر
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Microprocessors, Cache memory, Low-power electronics, Pipeline processing, Data compression, Instruction sets, Microprocessadors, Memòria ràpida de treball (Informàtica)
وصف الملف: 10 p.
العلاقة: http://ieeexplore.ieee.org/document/898069Test/; Canal, R., Gonzalez, A., Smith, J. Very low power pipelines using significance compression. A: Annual IEEE/ACM International Symposium on Microarchitecture. "33rd Annual ACM/IEEE International Symposium on Microarchitecture: MICRO-33, 2000: 10-13 december 2000: Monterey, California, USA: proceedings". Monterey, California: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 181-190.; 0-7695-0924-X; http://hdl.handle.net/2117/101915Test
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89رسالة جامعية
المؤلفون: Calin, Gabriel
مرشدي الرسالة: Obac Roda, Valentin
مصطلحات موضوعية: Lógica programável, Pipeline processing, Processamento em tempo-real, Processamento pipeline, Programmable logic, Real-time processing, Stereo vision, Visão estereoscópica
وصف الملف: application/pdf
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90مؤتمر
المؤلفون: Sánchez, Jesús, González Colás, Antonio María
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Software architecture, Prefetching, Delay, Processor scheduling, Pipeline processing, Registers, VLIW, Proposals, Degradation, Argon, Programari -- Disseny
وصف الملف: 2 p.
العلاقة: http://ieeexplore.ieee.org/document/649285Test/; Sánchez, J., Gonzalez, A. Software prefetching for software pipelined loops. A: Hawaii International Conference on System Sciences. "Proceedings of the Thirty-First Hawaii International Conference on System Sciences, vol. VII: Software technology track". Kohala Coast, Big Island, Hawai: Institute of Electrical and Electronics Engineers (IEEE), 1998, p. 778-779.; 0-8186-8251-5; http://hdl.handle.net/2117/105151Test
