-
1مؤتمر
المساهمون: Bettoni, Marco, Urgese, Gianvito, Kobayashi, Yuki, Macii, Enrico, Acquaviva, Andrea
مصطلحات موضوعية: CNN, FPGA, Alex-Net, Convolutional Neural Network, CNN on FPGA, High Level Synthesis, Field programmable gate arrays, Convolution, Random access memory, Graphics processing units, Computer architecture, Pipeline processing
وصف الملف: ELETTRONICO
العلاقة: info:eu-repo/semantics/altIdentifier/isbn/978-1-5090-6447-2; info:eu-repo/semantics/altIdentifier/wos/WOS:000426111600013; ispartofbook:Proceedings of IEEE International Conference on New Generation of CAS (NGCAS 2017); New Generation of Circuits and Systems NGCAS 2017; firstpage:49; lastpage:52; numberofpages:4; http://hdl.handle.net/11583/2687168Test; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-85034447110; http://ieeexplore.ieee.org/document/8052266Test/
الإتاحة: https://doi.org/10.1109/NGCAS.2017.16Test
http://hdl.handle.net/11583/2687168Test
http://ieeexplore.ieee.org/document/8052266Test/ -
2دورية أكاديمية
المؤلفون: Birgani, Yahya Arzani, Timarchi, Somayeh, Khalid, Ayesha
المصدر: Birgani , Y A , Timarchi , S & Khalid , A 2022 , ' Area-time-efficient scalable schoolbook polynomial multiplier for lattice-based cryptography ' , IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 69 , no. 12 , pp. 5079-5083 . https://doi.org/10.1109/TCSII.2022.3188943Test
مصطلحات موضوعية: Clocks, Computer architecture, Costs, Cryptography, DH-HEMTs, FPGA, Lattice-based cryptography (LBC), parallel, Pipeline processing, Random access memory, scalable, schoolbook polynomial multiplication (SPM), /dk/atira/pure/subjectarea/asjc/2200/2208, name=Electrical and Electronic Engineering
الإتاحة: https://doi.org/10.1109/TCSII.2022.3188943Test
https://pure.qub.ac.uk/en/publications/b154d71d-a0e3-4c58-ad0a-8ab0779be6ceTest -
3
المؤلفون: Ray T. Chen, Zheng Zhao, Zhoufeng Ying, David Z. Pan, Jiaqi Gu, Chenghao Feng, Richard A. Soref
المصدر: IEEE Photonics Journal, Vol 12, Iss 6, Pp 1-11 (2020)
مصطلحات موضوعية: lcsh:Applied optics. Photonics, Computer science, Computation, Optical computing, Physics::Optics, 02 engineering and technology, 01 natural sciences, Power budget, 010309 optics, 020210 optoelectronics & photonics, 0103 physical sciences, logic circuits, 0202 electrical engineering, electronic engineering, information engineering, lcsh:QC350-467, Electrical and Electronic Engineering, optical logic devices, Electronic circuit, Combinational logic, Sequential logic, pipeline processing, business.industry, lcsh:TA1501-1820, Chip, Atomic and Molecular Physics, and Optics, electro-optic devices, Computer architecture, Photonics, business, lcsh:Optics. Light
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3b3056bdcc461773bed6eec6850c26c1Test
https://ieeexplore.ieee.org/document/9226470Test/ -
4
المؤلفون: Lan Huang, Kangping Wang, Dalin Li, Teng Gao, Zihao Wang
المصدر: Electronics, Vol 10, Iss 532, p 532 (2021)
Electronics
Volume 10
Issue 5مصطلحات موضوعية: Computer Networks and Communications, Computer science, Concurrency, functional programming, lcsh:TK7800-8360, Symmetric multiprocessor system, 02 engineering and technology, High-level synthesis, 0202 electrical engineering, electronic engineering, information engineering, Concurrent computing, Electrical and Electronic Engineering, Field-programmable gate array, field programmable gate arrays, Functional programming, pipeline processing, parallel programming, lcsh:Electronics, 020207 software engineering, 020202 computer hardware & architecture, Data flow diagram, Computer architecture, Hardware and Architecture, Control and Systems Engineering, Signal Processing, Software design pattern, Programming paradigm, C++ template
وصف الملف: application/pdf
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ef6565574cef5c8b1ad0d026c82cc608Test
https://www.mdpi.com/2079-9292/10/5/532Test -
5مؤتمر
المؤلفون: Sánchez Carracedo, Fermín, Cortadella, Jordi
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament de Ciències de la Computació, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions, Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Informàtica teòrica, Microprocessors -- Programming, Parallel algorithms, Pipeline processing, Throughput, Processor scheduling, Iron, Computer architecture, Resource management, Costs, Timing, Delay effects, Registers, Microprocessadors -- Programació, Algorismes paral·lels
وصف الملف: 5 p.
العلاقة: https://ieeexplore.ieee.org/document/480177Test; Sánchez, F.; Cortadella, J. Time-constrained loop pipelining. A: IEEE/ACM International Conference on Computer-Aided Design. "Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995: San Jose, California, USA, November 5-9, 1995". Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 592-596.; 0-8186-7213-7; http://hdl.handle.net/2117/133457Test
-
6
المؤلفون: Enrico Macii, Yuki Kobayashi, Gianvito Urgese, Marco Bettoni, Andrea Acquaviva
المساهمون: BETTONI, MARCO, URGESE, GIANVITO, Kobayashi, Yuki, MACII, Enrico, ACQUAVIVA, ANDREA
المصدر: NGCAS
مصطلحات موضوعية: High Level Synthesis, Computer science, Convolutional Neural Network, Convolutional neural network, CNN, FPGA, Alex-Net, Convolutional Neural Network, CNN on FPGA, High Level Synthesis, Field programmable gate arrays, Convolution, Random access memory, Graphics processing units, Computer architecture, Pipeline processing, Software portability, Software, High-level synthesis, Computer architecture, Field-programmable gate array, FPGA, Auxiliary memory, CNN on FPGA, High Level Synthesi, business.industry, Field programmable gate array, Field programmable gate arrays, Video processing, Random access memory, Convolution, Graphics processing unit, Pipeline processing, Embedded system, Key (cryptography), business, Graphics processing units, CNN, Alex-Net
وصف الملف: ELETTRONICO
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6b3bb270f071396901cc2d22728878a8Test
https://doi.org/10.1109/ngcas.2017.16Test -
7دورية أكاديمية
المؤلفون: Llosa Espuny, José Francisco, Ayguadé Parra, Eduard, González Colás, Antonio María, Valero Cortés, Mateo, Eckhardt, Jason
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Programació, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Parallel programming (Computer science), Computer architecture, Parallel programming, Pipeline processing, Processor scheduling, Program compilers, Programació en paral·lel (Informàtica), Arquitectura d'ordinadors
وصف الملف: 16 p.
العلاقة: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=910814Test; Llosa, J., Ayguadé, E., González, A., Valero, M., Eckhardt, J. Lifetime-sensitive modulo scheduling in a production environment. "IEEE transactions on computers", Març 2001, vol. 50, núm. 3, p. 234-249.; http://hdl.handle.net/2117/78910Test
-
8مؤتمر
المؤلفون: Mirzaei, M.Ali, Voisin, Vincent, Annovi, Alberto, Baulieu, Guillaume, Beretta, Matteo, Calderini, Giovanni, Citraro, Saverio, Crescioli, Francesco, Galbit, Geoffrey, Liberali, Valentino, Shojaii, Seyed Ruhollah, Stabile, Alberto, Tromeur, William, Viret, Sebastien
المساهمون: Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), Institut de Physique Nucléaire de Lyon (IPNL), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), ANR-13-BS05-0011,FastTrack,Développement d'un système électronique de reconstruction de traces pour les expériences du grand collisionneur de hadrons.(2013)
المصدر: 6th International Conference on Modern Circuits and Systems Technologies
https://hal.science/hal-01669640Test
6th International Conference on Modern Circuits and Systems Technologies, May 2017, Thessaloniki, Greece. pp.7937638, ⟨10.1109/MOCAST.2017.7937638⟩مصطلحات موضوعية: communication channel, FPGA, direct memory access, DMA, multigigabit transceiver, MGT, Field programmable gate arrays, Program processors, Linux, Computer architecture, Communication channels, Central Processing Unit, Standards, content-addressable storage, file organisation, firmware, parallel processing, pattern recognition, pipeline processing, public domain software, system-on-chip, heterogeneous computing system platform, high-performance pattern recognition application, Xilinx Zynq system on chip, SoC, associative memory chip, AM, mezzanine board, open source software, ARM CPU
جغرافية الموضوع: Thessaloniki, Greece
العلاقة: hal-01669640; https://hal.science/hal-01669640Test; INSPIRE: 1639117
-
9دورية أكاديمية
المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
مصطلحات موضوعية: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Cache memory, Computer architecture, Pipeline processing, Buffer storage, Performance evaluation, Memòria ràpida de treball (Informàtica), Arquitectura d'ordinadors
وصف الملف: 9 p.
العلاقة: http://ieeexplore.ieee.org/document/210179Test/; González, A., Llaberia, J. Reducing branch delay to zero in pipelined processors. "IEEE transactions on computers", Març 1993, vol. 42, núm. 3, p. 363-371.; http://hdl.handle.net/2117/101127Test
-
10
المؤلفون: M. Beretta, Guillaume Baulieu, Saverio Citraro, M Ali Mirzaei, Vincent Voisin, William Tromeur, Seyed Ruhollah Shojaii, Francesco Crescioli, Valentino Liberali, G. Galbit, G. Calderini, Alberto Annovi, Alberto Stabile, Sébastien Viret
المساهمون: Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), Institut de Physique Nucléaire de Lyon (IPNL), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), Centre National de la Recherche Scientifique (CNRS)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)
المصدر: 6th International Conference on Modern Circuits and Systems Technologies
6th International Conference on Modern Circuits and Systems Technologies, May 2017, Thessaloniki, Greece. pp.7937638, ⟨10.1109/MOCAST.2017.7937638⟩
MOCASTمصطلحات موضوعية: high-performance pattern recognition application, Engineering, Standards, parallel processing, Motherboard, communication channel, public domain software, DMA, computer.software_genre, open source software, mezzanine board, firmware, associative memory chip, system-on-chip, System on a chip, [INFO]Computer Science [cs], Computer architecture, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], direct memory access, Field-programmable gate array, Direct memory access, FPGA, field programmable gate arrays, Communication channels, heterogeneous computing system platform, pipeline processing, file organisation, Firmware, business.industry, multigigabit transceiver, Linux, pattern recognition, content-addressable storage, Pattern recognition, Program processors, ARM architecture, AM, Embedded system, MGT, Xilinx Zynq system on chip, Systems architecture, Artificial intelligence, Central processing unit, ARM CPU, SoC, business, computer, Computer hardware, Central Processing Unit
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5656507c3354ddac82e1f809470a60e3Test
https://hal.archives-ouvertes.fr/hal-01669640Test
