التفاصيل البيبلوغرافية
| العنوان: |
PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD-SiNx Stressing Layer. |
| المؤلفون: |
Wen-Shiang Liao, Yue-Gie Liaw, Mao-Chyuan Tang, Kun-Ming Chen, Sheng-Yi Huang, Peng, C.-Y., Chee Wee Liu |
| المصدر: |
IEEE Electron Device Letters; Jan2008, Vol. 29 Issue 1, p86-88, 3p, 3 Graphs |
| مصطلحات موضوعية: |
COMPLEMENTARY metal oxide semiconductors, DIGITAL electronics, LOGIC circuits, TRANSISTOR-transistor logic circuits, SILICON, ELECTRIC conductivity, ELECTRONIC circuits |
| مستخلص: |
In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been successfully fabricated. The performance improvements of devices with a gate length (Lg) of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least +50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows +32% current gain for Lg = 40 nm PMOS with the thinnest 9Å Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance. [ABSTRACT FROM AUTHOR] |
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| قاعدة البيانات: |
Complementary Index |
