In advanced node, FinFET processes provide power, performance, and area benefits over planar technologies. But a vexing problem aggravated by FinFET is the greater local device current density, which translates to an increased concern for signal and power rail metal electromigration reliability failures. There is a critical secondary effect, as well the thermal profile of the FinFET influences the temperature of the metal interconnect neighborhood, which accelerates the EM failure rate probability. For now, the thermal impact has been broadly mentioned in the sight of design house. Following foundary′s user guide, Cadence Voltus provides an accurate, powerful and flexible solution. Based on it, we want to check the impact of thermal on high datablock and do more investigation to improve the power planning structure.
