FPGAs (Field Programmable Gate Arrays) are proving to be an alternative for applications that require great processing power because they allow parallelism. Still, the high-level synthesis tools allow professionals without hardware knowledge to use FPGAs. However, this high-level tools do not allow to properly explore the parallelism because they are either based on sequential techniques or rely on languages with an insufficient level of abstraction. In this paper it is proposed the use of the Notification Oriented Paradigm (NOP) for Digital Hardware as a high-level synthesis tool. The NOP is a development technique that presents a new concept for designing and executing applications, based on rules and collaborative entities, which communicate through notifications in a parallel way. In order to allow the use of the NOP in the creation of digital hardware as a new high-level synthesis tool, a new programming language was proposed, and both a compiler and an emulator where implemented. With these tools it is possible to generate VHDL code directly from a high level NOP program. In order to evaluate the performance and stability of circuits generated with these tools, some experiments were performed. These experiments demonstrated that the NOP for Digital Hardware allows quickly and easily creating reliable digital circuits with suitable performance and parallelism, directly from a high-level development environment.
