المؤلفون: Joshua A. Bell, Teja Singh, Stephen V. Kosonocky, Sundar Rangarajan, Shane Southard, Carson Henrion, Hugh McIntyre, Ravi Jotwani, Edward Chang, Amy Novak, Alex Schaefer, Deepesh John, Michael Co

المصدر: ISSCC

مصطلحات موضوعية: Engineering, business.industry, CPU cache, 020208 electrical & electronic engineering, Transistor, Process (computing), 02 engineering and technology, Voltage regulator, computer.software_genre, 020202 computer hardware & architecture, law.invention, law, Embedded system, Next-generation network, 0202 electrical engineering, electronic engineering, information engineering, Operating system, Cache, business, Distributed File System, computer, Voltage

الوصف: Codenamed “Zen”, AMD's next-generation, high-performance ×86 core targets server, desktop, and mobile client applications. Utilizing Global Foundries' energy-efficient 14nm LPP FinFET process, the 44mm2 Zen core complex unit (CCX) has 1.4B transistors and contains a shared 8MB L3 cache and four cores (Fig. 3.2.7). The 7mm2 Zen core contains a dedicated 0.5MB L2 cache, 32KB L1 data cache, and 64KB L1 instruction cache. Each core has a digital low drop-out (LDO) voltage regulator and digital frequency synthesizer (DFS) to independently vary frequency and voltage across power states.

الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_________::a1531050832f06532f78b6846da5e7c8Test
https://doi.org/10.1109/isscc.2017.7870256Test

المؤلفون: Teja Singh, Shane Southard, Joshua A. Bell

المصدر: ISSCC

مصطلحات موضوعية: Engineering, Power gating, CPU cache, business.industry, Parallel computing, Modular design, computer.software_genre, Power optimization, Power (physics), Low-power electronics, Operating system, x86, System on a chip, business, computer

الوصف: “Jaguar” (JG) is the codename for AMD's follow-on project to the low-power x86-64 core, codenamed “Bobcat” (BT). AMD's first 28nm × 86 processor, the 3.08mm2 JG core is designed to support a wide range of applications from low-power tablets requiring sub-5W SoCs to client products up to 25W. Similar to BT, the JG core uses integrated power gating to provide a low-power state for SOC power optimization. A JG compute unit (CU) is constructed using 4 JG cores, four 0.5MB L2 cache modules and an L2 interface (Fig. 3.4.1). An initial SOC has one 26.2mm2 CU, but AMD's modular design approach allows for different SOC configurations.

الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_________::b570c3c038fbc801d15ba6e3ef6655f7Test
https://doi.org/10.1109/isscc.2013.6487633Test