A modular parallel architecture for a MMSE-DFE coefficient computation processor is presented. The architecture is based on QR factorization of a channel-and-noise-dependent data matrix and is implemented using CORDIC processors within a systolic array architecture. Implementation issues including the number of CORDIC stages and the bit precision required in a fixed-point implementation are investigated through computer simulations. The proposed architecture accommodates fractionally spaced DFEs, co-channel interference, and multiple diversity paths.
