التفاصيل البيبلوغرافية
| العنوان: |
Implementation of A Dynamic Partial Reconfigurable Fpga Framework for Flexible Network on Chip |
| المؤلفون: |
Nguyễn Văn Cường*, Trần Thanh, Phạm Ngọc Nam |
| المصدر: |
The University of Danang - Journal of Science and Technology |
| بيانات النشر: |
University of Da Nang |
| سنة النشر: |
2015 |
| المجموعة: |
neliti (Indonesia's Think Tank Database) |
| مصطلحات موضوعية: |
cấu hình lại từng phần động, thiết bị nhúng, FPGA, DPR, NoC, Buffer, Embedded device, mạng trên chip, bộ đệm, bộ định tuyến, Indonesia, Router |
| الوصف: |
Flexibility and scalability are very important characteristics of modern embedded devices. The Dynamic Partial Reconfigurable (DPR) FPGA and Network on Chip (NoC) architectures are excellent solutions to these requirements. In this paper, we design a dynamic partial reconfigurable model based on FPGA for Network on Chip. The aim of this study is to perform the buffer size reconfiguration in the router at run-time adapted to the traffic state of applications that are used for the network in order to optimize some parameters such as lateness, throughput or energy consumption. This model is implemented and tested on Virtex-6 XC6VLX240T FPGA with both AXI and PLB Buses. |
| نوع الوثيقة: |
article in journal/newspaper |
| وصف الملف: |
application/pdf |
| اللغة: |
Indonesian |
| العلاقة: |
https://www.neliti.com/publications/452487/implementation-of-a-dynamic-partial-reconfigurable-fpga-framework-for-flexible-nTest |
| الإتاحة: |
https://www.neliti.com/publications/452487/implementation-of-a-dynamic-partial-reconfigurable-fpga-framework-for-flexible-nTest |
| حقوق: |
(c) The University of Danang - Journal of Science and Technology, 2015 |
| رقم الانضمام: |
edsbas.31BE496C |
| قاعدة البيانات: |
BASE |
