Parallel implementation of video encoder on quad DSP system

التفاصيل البيبلوغرافية
العنوان: Parallel implementation of video encoder on quad DSP system
المؤلفون: O. Lehtoranta, Timo Hämäläinen, Juha Mustonen, Ville Lappalainen
المصدر: Microprocessors and Microsystems. 26:1-15
بيانات النشر: Elsevier BV, 2002.
سنة النشر: 2002
مصطلحات موضوعية: Artificial Intelligence, Computer Networks and Communications, Hardware and Architecture, business.industry, Computer science, business, Frame rate, Encoder, Software, Computer hardware, Digital signal processing
الوصف: Implementation of H.263/MPEG4 video encoder is presented for a demanding vehicle remote control system. Required features are CIF-sized images, over 25 fps frame rate and flexibility to realize different coding modes and algorithms. A fully DSP-based implementation is chosen, in which the number of processors is scaleable. Out of parallel mapping approaches, a column-wise data parallel method in a master–slave configuration is chosen. A detailed performance analysis shows that the requirements are clearly exceeded with two TMS320C6201 processors while obtaining over 90% parallelization efficiency. Estimations are also given for a larger number of DSPs and image sizes.
تدمد: 0141-9331
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_________::3b7a2125d2f4c0ba8c907e93a0b3a20dTest
https://doi.org/10.1016/s0141-9331Test(01)00141-7
حقوق: CLOSED
رقم الانضمام: edsair.doi...........3b7a2125d2f4c0ba8c907e93a0b3a20d
قاعدة البيانات: OpenAIRE