التفاصيل البيبلوغرافية
| العنوان: |
Gate-stack optimization of a vertically stacked nanosheet FET for digital/analog/RF applications. |
| المؤلفون: |
Tayal, Shubham, Bhattacharya, Sandip, Ajayan, J., Thoutam, Laxman Raju, Muchahary, Deboraj, Jadav, Sunil, Krishan, Bal, Nizamuddin, M. |
| المصدر: |
Journal of Computational Electronics; Jun2022, Vol. 21 Issue 3, p608-617, 10p |
| مستخلص: |
Nanosheet field effect transistors (NS-FET) are a most promising candidate for next-generation semiconductor devices for sub-7-nm technology nodes. This work explores a two-channel vertically stacked NS-FET from a digital and analog/RF perspective. The influence of high-κ gate oxide is investigated with respect to the NS-FET-based CMOS inverter and RF/analog parameters of the NS-FET. It is found that the high-κ gate oxide does not change the performance of the NS-FET-based CMOS inverter significantly. Moreover, the proposed NS-FET at LC = 12 nm exhibits Ion, Ion/Ioff, and subthreshold swing (SS) of 646 µA/µm, 1.24 × 107, and 68.8 mV/dec, respectively, for a SiO2 gate dielectric and 779 µA/µm, 2.5 × 107, and 70 mV/dec, respectively, for a TiO2 gate dielectric. However, the high-κ gate oxide leads to deterioration in RF/analog parameters of the NS-FET, particularly in weak/moderate regions of operation. To overcome the deterioration caused by the high-κ gate oxide, nanosheet thickness (TNS), channel length (LC), and spacer dielectric material are optimized. It is revealed that the degradation in RF/analog parameters can be reduced by considering a thicker TNS (10 nm), lower LC (8 nm), and low-κ spacer dielectric (SiO2). [ABSTRACT FROM AUTHOR] |
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| قاعدة البيانات: |
Complementary Index |
