التفاصيل البيبلوغرافية
| العنوان: |
SOI high-voltage LDMOS with novel triplelayer top silicon based on thin BOX. |
| المؤلفون: |
Hu, S. D., Zhang, L., Luo, J., Tan, K. Z., Chen, W. S., Gan, P., Zhou, X.C., Zhu, Z. |
| المصدر: |
Electronics Letters (Wiley-Blackwell); 1/31/2013, Vol. 49 Issue 3, p18-19, 2p, 1 Diagram, 2 Charts, 2 Graphs |
| مصطلحات موضوعية: |
SILICON, ELECTRIC fields, HIGH voltages, DIELECTRICS, ELECTRIC breakdown |
| مستخلص: |
A novel SOI high-voltage LDMOS with a triple-layer top silicon (TLTS) is investigated. The top silicon layer of the TLTS LDMOS consists of n - silicon with a p-top layer, p - silicon in the middle, and n + silicon on the interface. On the condition of high-voltage blocking state, the electric fields of the drift region and BOX are modulated and optimised by the triple-layer top silicon, respectively, which induces a high BV of 624 V for the TLTS LDMOS with a thin buried oxide layer (BOX) of 0.4 μm. Compared with several SOI devices, the proposed TLTS LDMOS has a higher figure-of-merit. [ABSTRACT FROM AUTHOR] |
|
Copyright of Electronics Letters (Wiley-Blackwell) is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) |
| قاعدة البيانات: |
Complementary Index |
Full Text Finder