Research and Device Development of Residence Time Testing Technology for Network Acquisition Switch Based on Large Scale FPGA

التفاصيل البيبلوغرافية
العنوان: Research and Device Development of Residence Time Testing Technology for Network Acquisition Switch Based on Large Scale FPGA
المؤلفون: Niu Jian, Zhen Jialin, Zhu Xianbao, Zhou Kun, Liu Haitao
المصدر: 2019 IEEE 8th International Conference on Advanced Power System Automation and Protection (APAP).
بيانات النشر: IEEE, 2019.
سنة النشر: 2019
مصطلحات موضوعية: Engineering, business.industry, 020209 energy, Reliability (computer networking), Sample (statistics), 02 engineering and technology, Residence time (fluid dynamics), Power (physics), Models of communication, Transfer (computing), 0202 electrical engineering, electronic engineering, information engineering, Calibration, business, Field-programmable gate array, Computer hardware
الوصف: With the development of smart substation technology, the advantages of intelligent switch networking to transfer SV sample values have been widely recognized. A residence time test technology based on large-scale FPGA is proposed in order to accurately and conveniently test the residence time calibration performance of the intelligent substation dedicated switch. The large-scale FPGA technology is applied to the development of the smart substation network tester according to the IEC61850 communication model and the technical specification of the power dedicated switch. The device enables long-term online monitoring of the performance of the power switch's residence time calibration. The actual test results of the project show that the test device has high reliability and practicability.
الوصول الحر: https://explore.openaire.eu/search/publication?articleId=doi_________::fa91b22fae5a9e743c12521b914878c6Test
https://doi.org/10.1109/apap47170.2019.9225185Test
حقوق: CLOSED
رقم الانضمام: edsair.doi...........fa91b22fae5a9e743c12521b914878c6
قاعدة البيانات: OpenAIRE