مؤتمر
1 GHz fully pipelined 3.7 ns address access time 8 k×1024 embedded DRAM macro.
| العنوان: | 1 GHz fully pipelined 3.7 ns address access time 8 k×1024 embedded DRAM macro. |
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| المؤلفون: | Takahashi, O., Dhong, S., Ohkubo, M., Onishi, S., Dennard, R., Hannon, R., Crowder, S., Iyer, S., Wordeman, M., Davari, B., Weinberger, W.B., Aoki, N. |
| المصدر: | 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056); 2000, p396-397, 2p |
| قاعدة البيانات: | Complementary Index |
| ردمك: | 9780780358539 |
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| DOI: | 10.1109/ISSCC.2000.839831 |