In this paper, we propose the design and development of verification IP (VIP) of STBUS, a widely used bus protocol from STMicroelectronics [1]. VIP is a standalone, pre-verified and built-in verification infrastructure, which can be easily plugged in the simulation-based tests. We have followed Universal Verification Methodology (UVM) for the modelling of the STBUS VIP. Firstly we have verified the important properties of the STBUS protocol and made the VIP. Then we have shown how to use the VIP in a SoC to verify IPs.
