Patent
Output interface circuits
| العنوان: | Output interface circuits |
|---|---|
| Patent Number: | 4,353,104 |
| تاريخ النشر: | October 05, 1982 |
| Appl. No: | 06/274,372 |
| Application Filed: | June 17, 1981 |
| مستخلص: | In an interface circuit having a plurality of MOS FETs and connected between an input terminal and an external circuit for converting a MOS logic level signal into a TTL level signal, there are provided a delay circuit, a capacitor impressed with a signal delayed by the delay circuit, a potential holding circuit, and a protective circuit for preventing damage to the MOS FETs in the potential holding circuit. |
| Inventors: | Takayuki, Tanaka (Tokyo, JPX) |
| Assignees: | Oki Electric Industry Co., Ltd. (Tokyo, JPX) |
| Claim: | What is claimed is |
| Claim: | 1. An output interface circuit comprising |
| Claim: | a first MOS FET having a source electrode, a drain electrode connected to a first MOS level signal input terminal, and a gate electrode connected to a first source of fixed voltage; |
| Claim: | a second MOS FET having a source electrode, a drain electrode connected to a second MOS level signal input terminal, and a gate electrode connected to said first source of fixed voltage; |
| Claim: | a third MOS FET having a source electrode connected to a first output terminal, a gate electrode connected to the source electrode of said first MOS FET, and a drain electrode connected to a first start signal input terminal; |
| Claim: | a fourth MOS FET having a source electrode connected to a second output terminal, a gate electrode connected to the source electrode of said second MOS FET, and a drain electrode connected to said first start signal input terminal; |
| Claim: | a first capacitor connected between the gate and source electrodes of said third MOS FET; |
| Claim: | a second capacitor connected between the gate and source electrodes of said fourth MOS FET; |
| Claim: | a first transfer gate circuit for executing a NOR logic function of a reset signal and a signal at said second output terminal, and having an output terminal connected to said first output terminal; |
| Claim: | a second transfer gate circuit for executing a NOR logic function of said reset signal and the signal at said first output terminal and having an output terminal connected to said second output terminal; |
| Claim: | an output circuit for selectively converting signals at said first and second output terminals into a TTL level output signal; |
| Claim: | a delay circuit supplied with said signals at said first and second output terminals for outputting a delayed signal corresponding to a logic "1" of said output signal of said output circuit in accordance with a second start signal inputted thereto earlier than said first start signal; |
| Claim: | a third capacitor connected between an output terminal of said delay circuit and said second output terminal; |
| Claim: | a level holding circuit comprising a capacitor and a pair of MOS FETs for compensating for a decrease in a gate potential of said fourth MOS FET, said level holding circuit being connected across said second capacitor so as to render said fourth MOS FET nonconductive; and |
| Claim: | a protective circuit means, operatively connected to said pair of MOS FETs in said level holding circuit for preventing damage to said MOS FETs in said level holding circuit by limiting the voltage levels thereof. |
| Claim: | 2. An output interface circuit comprising |
| Claim: | a second MOS FET having a source electrode, a drain electrode connected to a second MOS Level signal input terminal, and a gate electrode connected to said first source of fixed voltage; |
| Claim: | third and fourth feedback capacitors connected between an output terminal of said delay circuit and said first and second output terminals respectively; |
| Claim: | a first level holding circuit comprising a capacitor and a pair of MOS FETs for compensating for a decrease in a gate potential of said third MOS FET, said first level holding circuit being connected across said first capacitor so as to render said third MOS FET nonconductive; |
| Claim: | a first protective circuit means, operatively connected to said pair of MOS FETs in said first level holding circuit for preventing damage to said pair of MOS FETs in said first level holding circuit by limiting the voltage levels thereof; |
| Claim: | a second level holding circuit comprising another capacitor and another pair of MOS FETs for compensating for a decrease in a gate potential of said fourth MOS FET, said second level holding circuit being connected across said second capacitor so as to render said fourth MOS FET nonconductive; and |
| Claim: | a second protective circuit means, operatively connected to said another pair of MOS FETs in said second level holding circuit for preventing damage to said another pair of MOS FETs in said second level holding circuit by limiting the voltage levels thereof. |
| Current U.S. Class: | 361/91; 307/475; 361/101 |
| Current International Class: | H02H 320 |
| Patent References Cited: | 3796893 March 1974 Hoffman et al. 3835457 September 1974 Yu 4214175 July 1980 Chan |
| Other References: | Toshio Wada et al., "A 64K.times.1 Bit Dynamic ED-MOS RAM", IEEE Journal of Solid-State Circuits, vol. Sc-13, No. 5, Oct. 1978, pp. 600-606. Toshio Wada et al., "A 15-ns 1024-Bit Fully Static MOS Ram", IEEE Journal of Solid-State Circuits, vol. Sc-13, No. 5, Oct. 1978, pp. 635-639. |
| Primary Examiner: | Eisenzopf, Reinhard J. |
| Attorney, Agent or Firm: | Wenderoth, Lind & Ponack |
| رقم الانضمام: | edspgr.04353104 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |