Patent
Semiconductor memory device
| العنوان: | Semiconductor memory device |
|---|---|
| Patent Number: | 9,935,108 |
| تاريخ النشر: | April 03, 2018 |
| Appl. No: | 15/282208 |
| Application Filed: | September 30, 2016 |
| مستخلص: | A semiconductor memory device includes stacks on a substrate, each of the stacks including word lines stacked on the substrate and first and second string selection lines laterally spaced apart from each other, vertical pillars passing through the stacks, and first and second bit lines extending longitudinally in a first direction and alternatingly arranged in a second direction crossing the first direction. In a plan view, at least two adjacent ones of the first bit lines in the second direction and at least one of the second bit lines overlap each vertical pillar. A distance between a center of the vertical pillar and one of the first bit lines is different from that between the center of the vertical pillar and another of the first bit lines. |
| Inventors: | Kim, Chul-Ho (Seoul, KR); Park, Seunghak (Seoul, KR); Kim, Sihyun (Seoul, KR); Kim, Cheolhong (Yongin-si, KR); Lee, Hunkook (Hwaseong-si, KR); Jung, Yongju (Hwaseong-si, KR) |
| Assignees: | Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR) |
| Claim: | 1. A semiconductor memory device, comprising: a substrate; stacks on the substrate, the stacks comprising word lines disposed one on another and first and second string selection lines laterally spaced apart from each other; vertical pillars passing through the stacks; and first bit lines and second bit lines extending longitudinally in a first direction, wherein the first bit lines are alternatingly disposed with the second bit lines in a second direction crossing the first direction, with respect to each of the vertical pillars, at least two of the first bit lines which are adjacent to each other in the second direction, and each of the second bit lines which is interposed between adjacent ones of said at least two of the first bit lines overlap the vertical pillar in a plan view of the vertical pillars and bit lines, and a shortest distance in the second direction between an axial center of each of the vertical pillars and one of the first bit lines overlapping the vertical pillar is different from a shortest distance in the second direction between the axial center of the vertical pillar and another of the first bit lines overlapping the vertical pillar. |
| Claim: | 2. The device of claim 1 , further comprising: a first separation structure extending in the second direction between the stacks; and a second separation structure extending in the second direction between the first and second string selection lines. |
| Claim: | 3. The device of claim 2 , wherein the vertical pillars comprise: first vertical pillars passing through the stacks, the first vertical pillars electrically coupled with the first string selection lines; and second vertical pillars passing through the stacks, the second vertical pillars electrically coupled with the second string selection lines, wherein the semiconductor memory device further comprises: first auxiliary lines extending across the first separation structure, each of the first auxiliary lines electrically connecting one of the first vertical pillars and one of the second vertical pillars; and second auxiliary lines extending across the second separation structure, each of the second auxiliary lines electrically connecting one of the first vertical pillars and one of the second vertical pillars. |
| Claim: | 4. The device of claim 3 , wherein the first auxiliary lines are arrayed in the second direction, the second auxiliary lines are arrayed in the second direction, the first bit lines are connected to the first auxiliary lines, respectively, and the second bit lines are connected to the second auxiliary lines, respectively. |
| Claim: | 5. The device of claim 3 , wherein the first auxiliary lines have first protrusions, which protrude in the second direction and overlie the first separation structure, the second auxiliary lines comprise second protrusions which overlie the second separation structure, and the first protrusions protrude in a direction opposite to the second protrusions. |
| Claim: | 6. The device of claim 3 , wherein each of the first auxiliary lines comprises first bridges disposed on the first vertical pillars, respectively, and a first protrusion interposed between the first bridges, and each of the second auxiliary lines comprises second bridges disposed on the second vertical pillars, respectively, and a second protrusion interposed between the second bridges, wherein the first protrusion protrudes in the second direction, the second protrusion protrudes in a direction opposite to the first protrusion, and an angle subtended by the first bridges and the first protrusion is different from an angle subtended by the second bridges and the second protrusion. |
| Claim: | 7. The device of claim 6 , wherein the angle subtended by the first bridges and the first protrusion is greater than the angle subtended by the second bridges and the second protrusion. |
| Claim: | 8. The device of claim 1 , further comprising dummy vertical pillars interposed between the first and second string selection lines and passing through one of the stacks. |
| Claim: | 9. The device of claim 1 , further comprising lower contacts disposed on the vertical pillars, respectively, wherein an axial center of each of the vertical pillars coincides with that of the lower contact disposed thereon, in a plan view of the lower contacts and vertical pillars. |
| Claim: | 10. The device of claim 1 , wherein each of the second bit lines has mirror symmetry about a plane that is parallel to the first direction and is spaced apart from the axial center of the vertical pillar overlapped by the second bit line. |
| Claim: | 11. A semiconductor memory device, comprising: a substrate; stacks on the substrate, the stacks comprising word lines disposed one on another and first and second string selection lines laterally spaced apart from each other in a first direction; a first separation structure extending in a second direction and comprising an insulating separation layer between the first and second string selection lines, and dummy vertical pillars passing through the insulating separation layer and one of the stacks; a second separation structure extending in the second direction between the stacks; active vertical pillars passing through the stacks; first auxiliary lines crossing the first separation structure, wherein each of the first auxiliary lines has a first protrusion and electrically connects respective ones of the vertical pillars which are adjacent to each other in the first direction; and second auxiliary lines crossing the second separation structure, wherein each of the second auxiliary lines has a second protrusion and electrically connects respective ones of the vertical pillars which are adjacent to each other in the first direction, wherein the first protrusion of each of the first auxiliary lines subtends an angle with an associated reference line passing through axial centers of the vertical pillars electrically connected by the first auxiliary line, and the second protrusion of each of the second auxiliary lines subtends an angle with an associated reference line passing through axial centers of the vertical pillars electrically connected by the second auxiliary line, in a plan view of the first and second auxiliary lines and vertical pillars, and the angle subtended by the first protrusion and the reference line associated therewith is different from the angle subtended by the second protrusion and the reference line associated therewith. |
| Claim: | 12. The device of claim 11 , wherein the first protrusion protrudes in a direction opposite to the second protrusion. |
| Claim: | 13. The device of claim 11 , wherein the first auxiliary lines are alternatingly disposed with the second auxiliary lines in the first direction, and a shortest one of lengths of the first auxiliary lines is greater than a shortest one of the lengths of the second auxiliary lines. |
| Claim: | 14. The device of claim 11 , wherein the first protrusion of each of the first auxiliary lines overlaps the second separation structure, and the second protrusion of each of the second auxiliary lines overlaps the first separation structure. |
| Claim: | 15. The device of claim 11 , further comprising first bit lines and second bit lines each extending longitudinally in the first direction, the first bit lines being alternatingly disposed with the second bit lines in the second direction, wherein with respect to each of the vertical pillars, at least two of the first bit lines which are adjacent to each other in the second direction, and each of the second bit lines which is interposed between adjacent ones of said at least two of the first bit lines overlap the vertical pillar in a plan view of the vertical pillars and bit lines. |
| Claim: | 16. A semiconductor memory device, comprising: a substrate; layers stacked one above another on the substrate and comprising a plurality of word lines; pillars extending vertically through the layers and arrayed in rows and columns extending in first and second directions, respectively, the pillars including a first pair of respective active ones of the pillars adjacent one another in the same row and a second pair of respective active ones of the pillars adjacent one another in the same row, the first pair of respective active ones of the pillars neighboring the second pair of respective active ones of the pillars in the first direction, and the active ones of the pillars of the first pair being spaced from one another in the first direction by a distance greater than that at which the active ones of the pillars of the second pair are spaced from one another; first bit lines and second bit lines extending longitudinally in one direction across the layers, wherein the first bit lines are alternatingly disposed with the second bit lines in a direction perpendicular to said one direction, a first auxiliary line spanning the pillars of the first pair and electrically connected thereto; and a second auxiliary line electrically spanning the pillars of the second pair, wherein the first auxiliary line bends between the pillars of the first pair in a plan view of the pillars and the auxiliary lines, and the first auxiliary line has a middle section that is overlapped by one of the first bit lines, said one of the first bit lines being electrically connected to the first auxiliary line at the middle section of the first auxiliary line, and the second auxiliary line bends between the pillars of the second pair in the plan view of the pillars and the auxiliary lines, and the second auxiliary line has a middle section that is overlapped by one of the second bit lines, said one of the second bit lines being electrically connected to the second auxiliary line at the middle section of the second auxiliary line. |
| Claim: | 17. The device of claim 16 , wherein the second auxiliary line bends to a lesser degree, as between the active ones of the pillars that it spans, than the first auxiliary line. |
| Claim: | 18. The device of claim 16 , wherein the first and second auxiliary lines bend in opposite directions parallel to the columns of the pillars. |
| Claim: | 19. The device of claim 18 , wherein each of the pillars is overlapped by at least three of the bit lines. |
| Claim: | 20. The device of claim 16 , further comprising isolation regions extending vertically through the stack of layers and dividing the stack of layers into sections arrayed in the first direction, wherein the pillars in each of the rows are offset from the pillars in each row of the pillars adjacent thereto such that the pillars of adjacent ones of the rows are disposed in a zigzagging pattern along the first direction, one of the sections of the stack of layers includes nine of the pillars disposed in the zigzagging pattern for each respective pair of adjacent ones of the rows of the vertical pillars, one of the nine pillars being a dummy pillar electrically isolated from the bit lines and the other eight of the vertical pillars being active ones of the pillars each electrically connected to one of the bit lines, the first auxiliary line crosses one of the isolation regions, and the second auxiliary line crosses a vertical plane passing through axial centers of the dummy pillars. |
| Patent References Cited: | 8092958 January 2012 Haffner 8169826 May 2012 Hishida et al. 8598712 December 2013 Huang et al. 9064735 June 2015 Kito et al. 9236340 January 2016 Lee et al. 9287167 March 2016 Seol et al. 9437605 September 2016 Chen 2015/0145014 May 2015 Shin et al. 2015/0194517 July 2015 Cheng et al. 2015/0194518 July 2015 Cheng et al. 1020130072671 July 2013 |
| Primary Examiner: | Lee, Kyoung |
| Attorney, Agent or Firm: | Volentine & Whitt, PLLC |
| رقم الانضمام: | edspgr.09935108 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |