A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is demonstrated. Using the short-gate concept [1], the ambipolar behavior of the TFET is successfully suppressed. The measured TFET performance is not yet beyond that of the MOSFET, most likely due to the use of silicon that has a large bandgap and the use of ion implantation for the formation of the tunnel junction which results in a low junction abruptness. To boost the device performance, a low thermal budget processing could be used on etched nanowires in a substrate with epitaxial grown junction, in order to increase the abruptness of the tunnel junction.
نوع الوثيقة:
conferencePaper
اللغة:
English
العلاقة:
Nanotechnology Workshop, Kyoto, Japan (13-14/6/2009)
