التفاصيل البيبلوغرافية
| العنوان: |
An 80MHz 4/spl times/ oversampled cascaded/spl Delta/spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR |
| المؤلفون: |
BOSI, ALESSANDRO, CASTELLO, RINALDO, PANIGADA, ANDREA, G. Cesura |
| المساهمون: |
Bosi, Alessandro, G., Cesura, Castello, Rinaldo, Panigada, Andrea |
| سنة النشر: |
2005 |
| المجموعة: |
IRIS UNIPV (Università degli studi di Pavia) |
| مصطلحات موضوعية: |
CMOS LOGIC CIRCUITS, ANALOGUE-DIGITAL CONVERSION, DELTA-SIGMA MODULATION, INTEGRATED CIRCUIT NOISE, LINEARISATION TECHNIQUES, PIPELINE PROCESSING, SIGNAL SAMPLING, /SPL DELTA//SPL SIGMA/ MODULATOR, 0.18 MICRON, 10 MHZ, 240 MW, 80 MHZ, CMOS CHIP, SFDR |
| الوصف: |
A 2/sup nd/-order 4b /spl Delta//spl Sigma/ modulator in cascade with a 9b pipeline clocked at 80MHz achieves 75dB DR, 74dB peak SNR and more than 87dB SFDR in a 10MHz bandwidth by means of background digital linearization and noise-cancellation algorithms. The 0.18/spl mu/m CMOS chip consumes 240mW including reference generator, digital decimator and correction logic |
| نوع الوثيقة: |
conference object |
| وصف الملف: |
STAMPA |
| اللغة: |
English |
| العلاقة: |
info:eu-repo/semantics/altIdentifier/isbn/9780780389045; ispartofbook:Digest of technical papers ISSCC; IEEE International Solid-State Circuits Conference; volume:1; firstpage:174; lastpage:175; numberofpages:2; http://hdl.handle.net/11571/23891Test; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-28144441360 |
| الإتاحة: |
http://hdl.handle.net/11571/23891Test |
| رقم الانضمام: |
edsbas.D6CF1ABB |
| قاعدة البيانات: |
BASE |
