A 65 nm CMOS analog processor with zero dead time for future pixel detectors

التفاصيل البيبلوغرافية
العنوان: A 65 nm CMOS analog processor with zero dead time for future pixel detectors
المؤلفون: Gaioni, L., Braga, D., Christian, D.C., Deptuch, G., Fahim, F., Nodari, B., Ratti, L., Re, V., Zimmerman, T.
المساهمون: AstroParticule et Cosmologie (APC (UMR_7164)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Observatoire de Paris, Université Paris Sciences et Lettres (PSL)-Université Paris Sciences et Lettres (PSL)-Centre National de la Recherche Scientifique (CNRS)-Université Paris Cité (UPCité)
المصدر: Nucl.Instrum.Meth.A ; 14th Vienna Conference on Instrumentation ; https://hal.science/hal-01554801Test ; 14th Vienna Conference on Instrumentation, Feb 2016, Vienna, Austria. pp.595-598, ⟨10.1016/j.nima.2016.04.053⟩
بيانات النشر: HAL CCSD
سنة النشر: 2016
المجموعة: HAL-CEA (Commissariat à l'énergie atomique et aux énergies alternatives)
مصطلحات موضوعية: Pixel detectors, Analog front-end, CMOS, Zero dead time processor, High-Luminosity LHC, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det]
جغرافية الموضوع: Vienna, Austria
الوصف: International audience ; Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm −2 s −1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.
نوع الوثيقة: conference object
اللغة: English
العلاقة: hal-01554801; https://hal.science/hal-01554801Test; INSPIRE: 1513605
DOI: 10.1016/j.nima.2016.04.053
الإتاحة: https://doi.org/10.1016/j.nima.2016.04.053Test
https://hal.science/hal-01554801Test
رقم الانضمام: edsbas.24FF53AA
قاعدة البيانات: BASE